1. Field of the Invention
The present invention relates to a Schmitt trigger circuit, and more particularly, to a Schmitt trigger circuit.
2. Discussion of the Related Art
Generally, a Schmitt trigger circuit maintains a uniform amplitude output voltage even when an input voltage increases or decreases around a threshold voltage. The uniform amplitude output voltage is maintained that is proportional to a hysteresis coefficient. Such a Schmitt trigger circuit may be used as an input buffer which stabilizes a pulse signal and prevents chattering and noise.
A conventional Schmitt trigger circuit will be described with reference to the accompanying drawings. FIG. 1 shows a conventional Schmitt trigger circuit. FIG. 2a and FIG. 2b are graphs illustrating trigger points of a conventional Schmitt trigger circuit.
The conventional Schmitt trigger circuit having a uniform trigger voltage includes a first PMOS transistor MP1, a second PMOS transistor MP2, a second NMOS transistor MN2, and a first NMOS transistor MN1. These transistors are connected to one another in series and connected to an input terminal in common. The conventional Schmitt trigger circuit also includes a third PMOS transistor MP3 and a third NMOS transistor MN3.
The second NMOS transistor MN2 is connected to the second PMOS transistor MP2 in series. The first PMOS transistor MP1 is connected to a power source voltage terminal. The first NMOS transistor MN1 is connected to a ground terminal. Each gate of the third PMOS transistor MP3 and the third NMOS transistor MN3 is in common and connected to a drain electrode and an output terminal of the second NMOS transistor MN2 and the second PMOS transistor MP2. A drain electrode of the third PMOS transistor MP3 is connected to a source electrode of the first PMOS transistor MP1, and a source electrode of MP3 is connected to the ground terminal. A source electrode of the third NMOS transistor MN3 is connected to a source electrode of the second NMOS transistor MN2, and a drain electrode of MN3 is connected to the power source voltage terminal.
The conventional Schmitt trigger circuit may be used as a modified buffer or inverter in which a direct current transition curve has a noise margin as compared to a general buffer or inverter in which a direct current transition curve has a logic threshold voltage when the input signal transitions from low to high or from high to low.
The operation of the conventional Schmitt trigger circuit will be described with reference to FIG. 2a and FIG. 2b.
As a transition of the input signal occurs from low to high, the output signal becomes high. If the input voltage increases to exceed the threshold voltage of the first NMOS transistor MN1, the first NMOS transistor MN1 is turned on to operate the third NMOS transistor MN3. Once the third NMOS transistor MN3 is turned on, a voltage is applied to the source electrode of the second NMOS transistor MN2. At this time, to turn on the second NMOS transistor MN2, the threshold voltage of the second NMOS transistor MN2 in addition to the voltage applied to the second NMOS transistor MN2 should be applied to the gate of the second NMOS transistor MN2 because the first NMOS transistor MN1 and the third NMOS transistor MN3 have a predetermined resistivity. If the input voltage continues to increase, the output voltage becomes low to the ground voltage through MN2 and MN1.
On the other hand, when the input signal transitions from high to low, the potential level of the input terminal continues to decrease to exceed the threshold voltage of the first PMOS transistor MP1. Thus, the first PMOS transistor MP1 is turned on to operate the third PMOS transistor MP3. Once the third PMOS transistor MP3 is turned on, the first PMOS transistor MP1 and the third PMOS transistor MP3 have a predetermined resistivity. In addition, a voltage is applied to the source electrode of second PMOS transistor MP2. At this time, the voltage as low as the threshold voltage should be applied to the gate of the second PMOS transistor MP2. If the input voltage continues to decrease, the first PMOS transistor MP1 and the second PMOS transistor MP2 pass the power source voltage and the output voltage is maintained at the potential of the power source voltage.
The conventional Schmitt trigger circuit has a predetermined noise margin in accordance with an adjustment of the trigger voltage by means of the first and third PMOS transistors MP1 and MP3 and the first and third NMOS transistors MN1 and MN3.
The conventional Schmitt trigger circuit has a uniform trigger voltage as illustrated in FIG. 2a and FIG. 2b. This voltage cannot be adjusted after the fabrication of the IC. In addition, when the trigger voltage of the IC needs to be adjusted, the IC must be replaced with another IC having the desired trigger voltage level.